For digital signal transmission, the lines of a typical PC board bus are long, thin conductors which extend relatively substantial lengths across the face of an insulating substrate, the substrate spacing each conductor from a ground plane and from other signal wires. As a result of this configuration, each line presents a significant capacitance which must be charged or discharged by a bus driver or similar circuit during data transmission. The result is substantial power consumption, particularly when a CMOS or TTL bus is driven between positive and negative power supply rails.
The power consumption resulting from parasitic bus line capacitance is affected negatively by data transmission rate across the bus line, as well as by line capacitance, the voltage swing on the driven line, and the driver supply voltage. The power loss may be expressed as P=f*(C)*(Vs*Vl), or f*C*V2, where P is the power loss through each conductor dissipated by the line driver, V is the voltage applied (where Vs is the driver supply voltage and Vl is the voltage swing), C is the capacitance of the driven line, conductor, and f is the frequency at which the line conductor is charged/discharged. If a driver output voltage swing exists from rail to rail, then Vs=Vl=V, and P=f*C*V2. It should also be noted that some additional small power consumption results from the resistance of each bus line. The reduction of voltage swing on a driven line is especially useful inside integrated circuits, and also applies to bipolar integrated circuits (bipolar transistors also require a small voltage to turn such the transistor ON).
One technique for reducing power consumption involves reducing the capacitance of the bus lines themselves. This option, however, requires that the fabrication process for chips and for circuit boards be modified. A change in process to reduce line capacitance is expensive and may adversely effect the fabrication of other circuitry on chips and boards. Another option is to reduce the frequency at which data is transferred across the bus. Assuming that the width of the bus is not increased, this option simply trades off system performance for power reduction, an option which usually is not viable in the design and implementation of high performance circuits.
If a line is driven by voltages, swinging between the potential of ground and the potential of the power supply, the most efficient method for the reduction of power dissipation has been to lower the supply voltage, since during a rail to rail swing the power dissipation is directly related to the square of the supply voltage. Another option has been to reduce the voltage swing of the signal driving a line, provided that a line receiver, at the remote end of the line can tolerate a reduced voltage swing at its input.
Power reduction also can be achieved by reducing the voltage swings experienced throughout the structure. By limiting voltage swings, it is possible to reduce the amount of power dissipated as the voltage at a node or on a line decays during a particular event or operation, as well as to reduce the amount of power required to return the various decayed voltages to the desired state after the particular event or operation, or prior to the next access.
As mentioned previously, there typically is a trade-off between power and speed, with faster signal rates and circuit response times usually dictating greater power requirements. Faster sense amplifiers can also tend to be physically larger, relative to low speed, low power devices. Furthermore, the analog nature of sense amplifiers can result in their consuming an appreciable fraction of the total power. Although one way to improve the responsiveness of a sense amplifier is to use a more sensitive sense amplifier, any gained benefits are offset by the concomitant circuit complexity which nevertheless suffers from increased noise sensitivity. It is desirable, then, to limit bitline voltage swings and to reduce the power consumed by the sense amplifier.